216AB61 HESG324013R0100 HESG435572P1

216AB61 HESG324013R0100 HESG435572P1 By accepting single-ended transformer or DC-coupled inputs, this board maintains the signal integrity of a wide variety of analog sources. Since its introduction to the market over a year ago, this product has opened up a range of frequencies and applications that were previously unattainable. It directly digitizes signal bandwidths up to nearly 900 MHz, allowing wideband radar and communications signals to be captured in a single channel rather than digitizing several smaller bandwidth segments. These protocols can act as masters or slaves and provide “exception reporting” capabilities and event dates (time stamps). Exception reporting allows the slave to “respond without receiving a request”. In a traditional master/slave scenario, the master device polls the slaves sequentially based on a previously defined order or specific requirements.

216AB61 HESG324013R0100 HESG435572P1 The on-board logic first demultiplexes the raw 2 GHz 10-bit A/D samples by a factor of eight to produce an 80-bit word at a reduced rate of 250 MHz for successful transfer to the FPGA, which then performs a variety of standard functions on the data, including memory transfers, formatting, triggering, gating, and transfer to the FPDP and VMEbus interfaces. The FPGA then performs a variety of standard functions on the data, including memory transfer, formatting, triggering, gating, and transfer to the FPDP and VMEbus interfaces. The FPGA also handles the switched serial fabric VXS interface using an on-chip RocketIO Gbit serial transceiver. Since most logic and DSP resources are not used for these factory functions, developers can utilize these parallel processing structures to implement custom signal processing algorithms and process captured data in real time.